The present invention relates to a semiconductor device having a vertical channel transistor, and more particularly, to a semiconductor device which is capable of using an entire space (width) between vertical channel transistors as a bit line region, without separating the space.
As the integration of semiconductor devices has increased, the channel length of transistors has gradually shrank. The reduction of the channel length causes a short channel effect, such as a drain induced barrier lowering (DIBL), a hot carrier effect, and a punch through.
To solve those shortcomings, various methods have been proposed. One exemplary method is to reduce a depth of a junction region or to increase a channel length by forming a recess channel for a transistor.
However, as the integration of semiconductor devices reaches Giga bits level, a general planar transistor structure having junction regions at both sides of a gate electrode has a difficulty in meeting a required device area even though a channel length is scaled down.
To solve the above-described limitations, a vertical channel transistor has been proposed.
A vertical channel transistor includes a gate and a buried bit line. The gate is formed to surround a vertical channel structure.
A general method for manufacturing a vertical channel transistor will be described below.
A photo process is performed to etch a cell region of a semiconductor substrate to a predetermined depth, thereby obtaining a top pillar, and a spacer surrounding a sidewall of the top pillar. Using the spacer as an etch mask, the exposed semiconductor substrate is further etched to form a trench, and an isotropic wet etch process is performed on the trench to form a neck pillar that integrally extends from the top pillar along a vertical direction. The neck pillar is formed to have a narrower width than the top pillar.
A surrounding gate including a gate insulating film and a gate conductive film is formed at an outer sidewall of the neck pillar. Then impurity ions are implanted into the semiconductor substrate adjacent to the surrounding gate, thereby obtaining a bit line impurity region. The semiconductor substrate is etched to a predetermined depth at which the impurity region is separated, thereby obtaining buried bit lines where the impurity region is separated. To prevent the buried bit lines from being electrically shorted, the semiconductor substrate is etched relatively deep.
Known subsequent processes are performed in sequence to complete the fabrication of a semiconductor device having a vertical channel transistor.
However, the method of separating the buried bit lines by etching the semiconductor substrate has a difficulty in securing a dimension necessary for processes, since a critical dimension of the buried bit lines is getting smaller because of higher integration of semiconductor devices.
Moreover, if a high-concentration ion implantation process is performed directly on a silicon substrate to form the buried bit lines, diffusion of impurities causes a body floating phenomenon. This results in degradation in performance of the transistor. On the other hand, if a doping concentration in the ion implantation process decreases, bit line resistance increases.